Carl-Johan H. Seger
8 references under this name, matched as it is written. Somebody else may write under it too, and the same person may appear here spelled another way.
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Carl-Johan H. Seger
Carl-Johan H. Seger, one of the two hands behind symbolic trajectory evaluation and later Intel formal verification. Five records, 1991 to 2015; the 1991 ternary-simulation paper spells him without the middle initial.
Word-level Symbolic Trajectory Evaluation
Supratik Chakraborty and others (2015)
Formal verification of iterative algorithms in microprocessors
Mark D. Aagaard and others (2000) · Proceedings - ACM IEEE Design Automation Conference · Association for Computing Machinery
Formally Verifying IEEE Compliance of Floating-Point Hardware
John W. O'Leary and others (1999) · Intel Technology Journal
Asynchronous Circuits
Janusz Brzozowski and others (1995) · Springer Nature
Formal verification by symbolic evaluation of partially-ordered trajectories
Carl-Johan H. Seger and others (1995) · Formal Methods in System Design · Springer Science+Business Media
Voss - a formal hardware verification system user's guide
Carl-Johan H. Seger (1993) · Technical Report 45
Formal Hardware Verification by Symbolic Ternary Trajectory Evaluation
Randal E. Bryant and others (1991) · Proceedings of the 28th ACM/IEEE Design Automation Conference (DAC '91)
A Characterization of Ternary Simulation of Gate Networks
J. A. Brzozowski and others (1987) · Institute of Electrical and Electronics Engineers (IEEE)