D. Giri

2 references under this name, matched as it is written. Somebody else may write under it too, and the same person may appear here spelled another way.

DECADES: A 67mm2, 1.46TOPS, 55 Giga Cache-Coherent 64-bit RISC-V Instructions per second, Heterogeneous Manycore SoC with 109 Tiles including Accelerators, Intelligent Storage, and eFPGA in 12nm FinFET

F. Gao and others (2023) · IEEE

Agile SoC development with open ESP: Invited paper

P. Mantovani and others (2020) · ACM