Dominique Borrione
4 references under this name, matched as it is written. Somebody else may write under it too, and the same person may appear here spelled another way.
An approach to the introduction of formal validation in an asynchronous circuit design flow
Dominique Borrione and others (2003) · IEEE
Formal semantics of VHDL timing constructs
Ashraf Salem and others (1992) · Springer US
Applications of a BDD-package to the verification of HDL descriptions
Dominique Borrione and others (1991) · Advanced Research Workshop on Correct Hardware Design Methodologies
PREVAIL: A proof environment for VHDL descriptions
Dominique Borrione and others (1991) · Advanced Research Workshop on Correct Hardware Design Methodologies