E.M. Clarke

2 references under this name, matched as it is written. Somebody else may write under it too, and the same person may appear here spelled another way.

Symbolic model checking for sequential circuit verification

J.R. Burch and others (1994) · Institute of Electrical and Electronics Engineers (IEEE)

Automatic verification of asynchronous circuits using temporal logic

D.L. Dill and others (1986) · Institution of Engineering and Technology (IET)