F. ur Rahman
2 references under this name, matched as it is written. Somebody else may write under it too, and the same person may appear here spelled another way.
A combined all-digital PLL-buck slack regulation system with autonomous CCM/DCM transition control and 82% average voltage-margin reduction in a 0.6-to-1.0V cortex-M0 processor
X. Sun and others (2018) · IEEE
Computational locking: Accelerating lock-times in all-digital PLLs
F. ur Rahman and others (2017) · IEEE