M. Martonosi

4 references under this name, matched as it is written. Somebody else may write under it too, and the same person may appear here spelled another way.

DECADES: A 67mm2, 1.46TOPS, 55 Giga Cache-Coherent 64-bit RISC-V Instructions per second, Heterogeneous Manycore SoC with 109 Tiles including Accelerators, Intelligent Storage, and eFPGA in 12nm FinFET

F. Gao and others (2023) · IEEE

RTLCheck: Verifying the memory consistency of RTL designs

Y. A. Manerkar and others (2017) · Proceedings of the 50th International Symposium on Microarchitecture (MICRO)

COATCheck: Verifying memory ordering at the hardware-OS interface

D. Lustig and others (2016) · Proceedings of the 21st International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS)

CCICheck: Using µhb graphs to verify the coherence-consistency interface

Y. A. Manerkar and others (2015) · Proceedings of the 48th International Symposium on Microarchitecture (MICRO)