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Thomas Bourgeat
A grouping.
Thomas Bourgeat: hardware verification for security and concurrency - contract shadow logic for secure speculation, sequentialising concurrent hardware verification, and pre-silicon information-flow tracking.
10 references
Efficient Hardware Information-Flow Tracking for Pre-Silicon Security Testing
Yu-Wei Fan and others (2026)
Making Concurrent Hardware Verification Sequential
Thomas Bourgeat and others (2025) · Proceedings of the ACM on Programming Languages
RTL Verification for Secure Speculation Using Contract Shadow Logic
Qinhan Tan and others (2025) · Proceedings of the 30th ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS 2025), Volume 1
Specification and Verification of Sequential Machines in Rule-Based Hardware Languages
Thomas Bourgeat (2023)
Metior: A Comprehensive Model to Evaluate Obfuscating Side-Channel Defense Schemes
Peter W. Deutsch and others (2023) · ACM
Effective simulation and debugging for a high-level hardware language using software compilers
Clément Pit-Claudel and others (2021)
CaSA: End-to-end Quantitative Security Analysis of Randomly Mapped Caches
Thomas Bourgeat and others (2020) · IEEE
Composable Building Blocks to Open up Processor Design
Sizhuo Zhang and others (2019) · IEEE Micro
Composable Building Blocks to Open up Processor Design
Sizhuo Zhang and others (2018) · IEEE
A multipurpose formal RISC-V specification, 2021.
Thomas Bourgeat and others