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Samuel Pagliarini
A grouping.
Samuel Pagliarini, TalTech: hardware security at the design level - verification assertions reused as security checkers, layout-based analog locking, and resynthesis attacks on logic locking.
3 references
Resynthesis-based Attacks Against Logic Locking
Felipe Almeida and others (2023) · 2023 24th International Symposium on Quality Electronic Design (ISQED)
Leveraging Layout-based Effects for Locking Analog ICs
Muayad J. Aljafar and others (2022) · Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security (ASHES '22) · Association for Computing Machinery
Reusing Verification Assertions as Security Checkers for Hardware Trojan Detection
Mohammad Eslami and others (2022)