This description was written by a machine and published without a person checking it. It is what the agent made of this grouping, and not a statement anybody has stood behind.
Where the wires go
A subject the papers are about. The loosest grouping, and the one to reach for last.
Physical design, where wires rather than gates decide the outcome: Rent's rule, interconnect delay, and the placement, routing and packaging that follow. Membership: the wires are the constraint.
13 references
Clock tree synthesis in modern VLSI: From foundational algorithms to AI-driven optimization
Manikandan B and others (2026) · Integration, the VLSI Journal · Elsevier
A Chisel Generator for Standardized 3-D Die-to-Die Interconnects
H. Liew and others (2024) · Institute of Electrical and Electronics Engineers (IEEE)
Global Is the New Local: FPGA Architecture at 5nm and Beyond
Stefan Nikolić and others (2021) · Proceedings of the 2021 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA '21) · Association for Computing Machinery
NetCracker: A Peek into the Routing Architecture of Xilinx 7-Series FPGAs
Morten B. Petersen and others (2021) · The 2021 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays · Association for Computing Machinery
RePlAce: Advancing Solution Quality and Routability Validation in Global Placement
C.K. Cheng and others (2018) · Institute of Electrical and Electronics Engineers (IEEE)
Quadratic timing objectives for incremental timing-driven placement optimization
Mateus Fogaca and others (2016) · 2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS) · IEEE
A New Clock Network Synthesizer for Modern VLSI Designs
Jingwei Lu and others (2012) · Integration, the VLSI Journal
VLSI Physical Design: From Graph Partitioning to Timing Closure
Andrew B. Kahng and others (2011) · Springer
Handbook of Algorithms for Physical Design Automation
Charles J. Alpert and others (2008) · CRC Press
The future of wires
R. Ho and others (2001) · Proceedings of the IEEE · Institute of Electrical and Electronics Engineers (IEEE)
Timing-driven placement for FPGAs
A. Marquardt and others (2000) · ACM
Vpr: a new packing, placement and routing tool for fpga research
Vaughn Betz and others (1997) · Field- Programmable Logic and Applications
On a Pin Versus Block Relationship For Partitions of Logic Graphs
B. S. Landman and others (1971) · IEEE Transactions on Computers · IEEE