This description was written by a machine and published without a person checking it. It is what the agent made of this grouping, and not a statement anybody has stood behind.
Where the wires go
A subject the papers are about. The loosest grouping, and the one to reach for last.
Turning a design into geometry, where the wires and not the gates decide the outcome. Collects the physical-design literature: Rent's rule and the interconnect-delay results that establish why wiring does not shrink as logic does, and the placement, routing and packaging work that follows from it. Membership turns on the wires being the constraint, not on the design being physical.
12 references
Clock tree synthesis in modern VLSI: From foundational algorithms to AI-driven optimization
Manikandan B and others (2026) · Integration, the VLSI Journal · Elsevier
Soft Embedded FPGA Fabrics: Top-down Physical Design & Applications
Prashanth Mohan (2022)
Evolutionary Standard Cell Synthesis of Unconventional Designs
Prashanth H. C. and others (2022) · Proceedings of the Great Lakes Symposium on VLSI 2022
A Composable Glitch-Aware Delay Model
Jürgen Maier and others (2021) · Proceedings of the Great Lakes Symposium on VLSI 2021 · Association for Computing Machinery
Top-down Physical Design of Soft Embedded FPGA Fabrics
Prashanth Mohan and others (2021) · Proceedings of the 2021 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA '21) · Association for Computing Machinery
Global Is the New Local: FPGA Architecture at 5nm and Beyond
Stefan Nikolić and others (2021) · Proceedings of the 2021 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA '21) · Association for Computing Machinery
NetCracker: A Peek into the Routing Architecture of Xilinx 7-Series FPGAs
Morten B. Petersen and others (2021) · The 2021 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays · Association for Computing Machinery
A New Clock Network Synthesizer for Modern VLSI Designs
Jingwei Lu and others (2012) · Integration, the VLSI Journal
VLSI Physical Design: From Graph Partitioning to Timing Closure
Andrew B. Kahng and others (2011) · Springer
Handbook of Algorithms for Physical Design Automation
Charles J. Alpert and others (2008) · CRC Press
The future of wires
R. Ho and others (2001) · Proceedings of the IEEE · Institute of Electrical and Electronics Engineers (IEEE)
On a Pin Versus Block Relationship For Partitions of Logic Graphs
B. S. Landman and others (1971) · IEEE Transactions on Computers · IEEE