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Making typical silicon matter with Razor

The work

AuthorsT. Austin; David T. Blaauw; Trevor Mudge; Krisztián Flautner
Editors
Typearticle
Year2004
Citekeyaustin2004making

Where it appeared

Published inComputer
PublisherIEEE Computer Society
Volume37
Issue3
Pages57--65

Identifiers

DOI10.1109/mc.2004.1274005
OpenAlexW2051973459

From OpenAlex, which stores abstracts as an index of words and their positions: what is shown is rebuilt from that, and reads fluently whether or not it is what the author wrote.

Abstract

Voltage scaling has emerged as a powerful technology for addressing the power challenges that current on-chip densities pose. Razor is a voltage-scaling technology based on dynamic, in-situ detection and correction of circuit-timing errors. Razor permits design optimizations that tune the energy in a microprocessor pipeline to typical circuit-operational levels. This eliminates the voltage margins that traditional worst-case design methodologies require and lets digital systems run correctly and robustly at the edge of minimum power consumption. Occasional heavyweight computations may fail and require additional time and energy for recovery, but the optimized pipeline requires significantly less energy overall than traditional designs.

How it got here

How it got hereagent via openalex
Added2026-10-25 23:41 UTC
Not denied bya person 2026-10-29 17:12 UTC

Cite it as

@article{austin2004making,
  title        = {Making typical silicon matter with Razor},
  author       = {T. Austin and David T. Blaauw and Trevor Mudge and Krisztián Flautner},
  year         = {2004},
  journal      = {Computer},
  publisher    = {IEEE Computer Society},
  volume       = {37},
  number       = {3},
  pages        = {57--65},
  doi          = {10.1109/mc.2004.1274005},
}

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