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Piranha: a scalable architecture based on single-chip multiprocessing
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Abstract
The microprocessor industry is currently struggling with higher development costs and longer design times that arise from exceedingly complex processors that are pushing the limits of instruction-level parallelism. Meanwhile, such designs are especially ill suited for important commercial applications, such as on-line transaction processing (OLTP), which suffer from large memory stall times and exhibit little instruction-level parallelism. Given that commercial applications constitute by far the most important market for high-performance servers, the above trends emphasize the need to consider alternative processor designs that specifically target such workloads. The abundance of explicit thread-level parallelism in commercial workloads, along with advances in semiconductor integration density, identify chip multiprocessing (CMP) as potentially the most promising approach for designing processors targeted at commercial servers.
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Cite it as
@misc{barroso2000piranha,
title = {Piranha: a scalable architecture based on single-chip multiprocessing},
author = {Luiz André Barroso and Kourosh Gharachorloo and Robert McNamara and Andreas G. Nowatzyk and Shaz Qadeer and Barton Sano and Scott F. Smith and Robert J. Stets and Ben Verghese},
year = {2000},
journal = {Proceedings - International Symposium on Computer Architecture/Proceedings},
pages = {282--293},
doi = {10.1145/339647.339696},
}