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Flot de conception et modèles formels pour la désynchronisation de circuits synchrones
In the smart-cards market, contactless communication becomes more and more common. In order to reduce the cost of the systems, the power budget available reduces along with the size reduction of the antenna. Many design techniques are available to improve the efficiency of digital design. However, asynchronous designs, because of their adaptability to variable operating conditions, offer a natural solution for the contactless power supply problematics. Nevertheless, the lack of engineers trained, and proven tools, to design asynchronous circuits brakes the adoption of asynchronous designs in the industry. To address these issues, a systematic method allowing to turn already existing synchronous designs into asynchronous micropipelines had been developed. Using a formal model, a desynchronization process was established and used on a cryptographic module which was implemented on silicon. The characterization of this circuit showed the benefits of desynchronization but also its limits. Since the efficiency of desynchronization depends strongly on the architecture of the synchronous circuit initially considered, the proposed flow allows the performance of the desynchronized circuit to be estimated quickly, and also yields a functional physical circuit.
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@phdthesis{bertrand2019flot,
title = {Flot de conception et modèles formels pour la désynchronisation de circuits synchrones},
author = {François Bertrand},
year = {2019},
school = {Université Grenoble Alpes},
}