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19.6 A 40-to-80MHz Sub-4μW/MHz ULV Cortex-M0 MCU SoC in 28nm FDSOI With Dual-Loop Adaptive Back-Bias Generator for 20μs Wake-Up From Deep Fully Retentive Sleep Mode
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Abstract
Near-threshold circuits operating at ultra-low voltage (ULV) have matured with integration in commercial products, such as ultra-low-power (ULP) MCUs for the IoT [1]. In this market, MCU design faces the key performance tradeoff between speed, active power, deep-sleep retention power and wakeup time, with the challenge of preserving it over PVT corners. We present a ULP MCU SoC in 28nm FDSOI codenamed SleepRunner, exploiting back-biasing (BB) capability of FDSOI to push the performance tradeoff beyond the state-of-the-art.
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Cite it as
@misc{bol2019196,
title = {19.6 A 40-to-80MHz Sub-4μW/MHz ULV Cortex-M0 MCU SoC in 28nm FDSOI With Dual-Loop Adaptive Back-Bias Generator for 20μs Wake-Up From Deep Fully Retentive Sleep Mode},
author = {David Bol and Maxime Schramme and Ludovic Moreau and Thomas Haine and Pengcheng Xu and Charlotte Frenkel and Rémi Dekimpe and François Stas and Denis Flandre},
year = {2019},
journal = {Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference},
publisher = {Institute of Electrical and Electronics Engineers},
pages = {322--324},
doi = {10.1109/isscc.2019.8662293},
}