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An approach to the formal verification of VHDL descriptions
The work
| Authors | D Borrione; J L Paillet |
|---|---|
| Editors | |
| Type | techreport |
| Year | 1987 |
| Citekey | borrione1987approach |
Where it appeared
| Publisher | Technical Report RR 683-I- |
|---|---|
| School | Technical Report RR 683-I- |
How it got here
| How it got here | agent via bibtex |
|---|---|
| Added | 2026-10-25 05:13 UTC |
| Not denied by | a person 2026-10-29 17:12 UTC |
Filed under
Cite it as
@techreport{borrione1987approach,
title = {An approach to the formal verification of VHDL descriptions},
author = {D Borrione and J L Paillet},
year = {1987},
publisher = {Technical Report RR 683-I-},
school = {Technical Report RR 683-I-},
}
This record lives at https://refs.drheap.org/borrione1987approach/ and will keep doing so.