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Incorporating efficient assertion checkers into hardware emulation

The work

AuthorsMarc Boulé; Z. Zilic
Editors
Typemisc
Year2005
Also known asboule2006incorporating
Citekeyboule2005incorporating

Where it appeared

Published inProceedings, IEEE International Conference on Computer Design/Proceedings - IEEE International Conference on Computer Design
PublisherInstitute of Electrical and Electronics Engineers
Pages221--228

Identifiers

DOI10.1109/iccd.2005.66
OpenAlexW2137974383

Access

Landing pagehttps://doi.org/10.1109/iccd.2005.66

From OpenAlex, which stores abstracts as an index of words and their positions: what is shown is rebuilt from that, and reads fluently whether or not it is what the author wrote.

Abstract

Assertion-based verification (ABV) is emerging as a paramount technique for industrial-strength hardware verification, especially through the emerging property specification language (PSL). Since PSL introduces significant overhead to simulators, in this paper we present the infrastructure for hardware emulation capable of supporting ABV. We develop a tool that generates hardware assertion checkers for inclusion into efficient circuit emulation. The MBAC checker generator is outlined, together with the algorithms for optimized assertion-circuit generation. Experiments show that MBAC outperforms the best known checker-generator.

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Added2026-10-26 02:43 UTC
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Cite it as

@misc{boule2005incorporating,
  title        = {Incorporating efficient assertion checkers into hardware emulation},
  author       = {Marc Boulé and Z. Zilic},
  year         = {2005},
  journal      = {Proceedings, IEEE International Conference on Computer Design/Proceedings - IEEE International Conference on Computer Design},
  publisher    = {Institute of Electrical and Electronics Engineers},
  pages        = {221--228},
  doi          = {10.1109/iccd.2005.66},
}

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