Processor- and memory-based checkpoint and rollback recovery
The work
| Authors | Nicholas S. Bowen; D.K. Pradham |
|---|---|
| Editors | |
| Type | article |
| Year | 1993 |
| Citekey | bowen1993processor |
Where it appeared
| Published in | Computer |
|---|---|
| Publisher | IEEE Computer Society |
| Volume | 26 |
| Issue | 2 |
| Pages | 22--31 |
Identifiers
| DOI | 10.1109/2.191981 |
|---|---|
| OpenAlex | W2054254680 |
Access
| Landing page | https://doi.org/10.1109/2.191981 |
|---|
From OpenAlex, which stores abstracts as an index of words and their positions: what is shown is rebuilt from that, and reads fluently whether or not it is what the author wrote.
Abstract
Several hardware-based techniques that support checkpoint and rollback recovery are presented. The focus is on hardware schemes for uniprocessors, shared-memory multiprocessors, and distributed virtual-memory systems. A taxonomy for processor and memory techniques based on the memory hierarchy is presented. This provides a basis for understanding subtle differences among the various schemes. Processor-based schemes that handle transient faults by using processor-based transparent rollback techniques and memory-based schemes that roll back data instead of instructions and can be integrated with the processor techniques or can be exploited by higher levels of software are discussed.>
How it got here
| How it got here | agent via openalex |
|---|---|
| Added | 2026-10-26 00:53 UTC |
| Not denied by | a person 2026-10-29 17:12 UTC |
Cite it as
@article{bowen1993processor,
title = {Processor- and memory-based checkpoint and rollback recovery},
author = {Nicholas S. Bowen and D.K. Pradham},
year = {1993},
journal = {Computer},
publisher = {IEEE Computer Society},
volume = {26},
number = {2},
pages = {22--31},
doi = {10.1109/2.191981},
}
This record lives at https://refs.drheap.org/bowen1993processor/ and will keep doing so.