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Synthèse automatisée de circuits asynchrones optimisés prouvés quasi insensibles aux délais
In an asynchronous circuit, the synchronization between the blocks is local: the constraints due to the clock do not apply. These circuits are more robust, modular, have less noise and a lower dynamic power consumption than synchronous circuits. However, the lack of design tools for such circuits prevents them from spreading widely. This thesis aimed at developing an automatic synthesis technique targeting asynchronous quasi delay insensitive (QDI) circuits, which are particularly robust. The technique synthesizes a circuit totally decomposed into elementary logic gates, which allows a later technology mapping. Moreover, a formal study done during this thesis proves that the circuits synthesized respect the constraint of quasi delay insensitivity. This synthesis technique was developed in the TAST project. It has been validated on a set of test circuits.
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@phdthesis{bregier2007synthese,
title = {Synthèse automatisée de circuits asynchrones optimisés prouvés quasi insensibles aux délais},
author = {Vivian Brégier},
year = {2007},
school = {Institut National Polytechnique de Grenoble},
}