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HADES: Microprocessor Hazard Analysis via Formal Verification of Parameterized Systems

The work

AuthorsLukáš Charvát; Aleš Smrčka; Tomáš Vojnar
Editors
Typearticle
Year2016
Citekeycharvat2016hades

Where it appeared

Published inElectronic Proceedings in Theoretical Computer Science
PublisherOpen Publishing Association
Volume233
Pages87--93

Identifiers

arXiv1612.04986 from its oa_pdf_url
DOI10.4204/eptcs.233.9
OpenAlexW2562688732

From OpenAlex, which stores abstracts as an index of words and their positions: what is shown is rebuilt from that, and reads fluently whether or not it is what the author wrote.

Abstract

HADES is a fully automated verification tool for pipeline-based microprocessors that aims at flaws caused by improperly handled data hazards. It focuses on single-pipeline microprocessors designed at the register transfer level (RTL) and deals with read-after-write, write-after-write, and write-after-read hazards. HADES combines several techniques, including data-flow analysis, error pattern matching, SMT solving, and abstract regular model checking. It has been successfully tested on several microprocessors for embedded applications.

How it got here

How it got hereagent via openalex
Added2026-10-26 11:13 UTC
Not denied bya person 2026-10-29 17:12 UTC

Filed under

eptcs

Cite it as

@article{charvat2016hades,
  title        = {HADES: Microprocessor Hazard Analysis via Formal Verification of Parameterized Systems},
  author       = {Lukáš Charvát and Aleš Smrčka and Tomáš Vojnar},
  year         = {2016},
  journal      = {Electronic Proceedings in Theoretical Computer Science},
  publisher    = {Open Publishing Association},
  volume       = {233},
  pages        = {87--93},
  doi          = {10.4204/eptcs.233.9},
}

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