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Property Learning Techniques for Efficient Generation of Directed Tests

The work

AuthorsMingsong Chen; Prabhat Mishra
Editors
Typearticle
Year2011
Citekeychen2011property

Where it appeared

Published inIEEE Transactions on Computers
PublisherInstitute of Electrical and Electronics Engineers
Volume60
Issue6
Pages852--864

Identifiers

DOI10.1109/tc.2011.49
OpenAlexW2167928566

From OpenAlex, which stores abstracts as an index of words and their positions: what is shown is rebuilt from that, and reads fluently whether or not it is what the author wrote.

Abstract

Property falsification in model checking is widely used for automated generation of directed tests. Due to state space explosion problem, traditional model checking techniques cannot handle large scale designs. SAT-based bounded model checking is promising to address the prohibitively large time and resource requirements during the property falsification. This article presents several efficient learning techniques that can improve the overall test generation time for a single property as well as a cluster of similar properties. The goal is to exploit both variable assignments and common conflict clauses of the prechecked partial or similar SAT instances for property falsification. Our method makes three novel contributions: 1) investigates the decision ordering-based learnings for a single SAT instance; 2) applies the decision ordering learnings between similar SAT instances; and 3) exploits the relation between the decision ordering-based learning and conflict clauses-based learning. Our experimental results using both software and hardware benchmarks demonstrate that our approach can drastically reduce the overall test generation time.

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Added2026-10-24 21:33 UTC
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Cite it as

@article{chen2011property,
  title        = {Property Learning Techniques for Efficient Generation of Directed Tests},
  author       = {Mingsong Chen and Prabhat Mishra},
  year         = {2011},
  journal      = {IEEE Transactions on Computers},
  publisher    = {Institute of Electrical and Electronics Engineers},
  volume       = {60},
  number       = {6},
  pages        = {852--864},
  doi          = {10.1109/tc.2011.49},
}

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