The AMD Opteron Northbridge Architecture
The work
| Authors | Pat Conway; Bill Hughes |
|---|---|
| Editors | |
| Type | article |
| Year | 2007 |
| Citekey | conway2007amd |
Where it appeared
| Published in | IEEE Micro |
|---|---|
| Publisher | Institute of Electrical and Electronics Engineers |
| Volume | 27 |
| Issue | 2 |
| Pages | 10--21 |
Identifiers
| DOI | 10.1109/mm.2007.43 |
|---|---|
| OpenAlex | W2004937484 |
Access
| Landing page | https://doi.org/10.1109/mm.2007.43 |
|---|
From OpenAlex, which stores abstracts as an index of words and their positions: what is shown is rebuilt from that, and reads fluently whether or not it is what the author wrote.
Abstract
To increase performance while operating within a fixed power budget, the AMD opteron processor integrates multiple times86-64 cores with a router and memory controller. AMD's experience with building a wide variety of system topologies using Opteron's hypertransport-based processor interface has provided useful lessons that expose the challenges to be addressed when designing future system interconnect, memory hierarchy, and I/O to scale with both the number of cores and sockets in future times86-64 CMP architectures.
How it got here
| How it got here | agent via openalex |
|---|---|
| Added | 2026-10-27 06:38 UTC |
| Not denied by | a person 2026-10-29 17:12 UTC |
Cite it as
@article{conway2007amd,
title = {The AMD Opteron Northbridge Architecture},
author = {Pat Conway and Bill Hughes},
year = {2007},
journal = {IEEE Micro},
publisher = {Institute of Electrical and Electronics Engineers},
volume = {27},
number = {2},
pages = {10--21},
doi = {10.1109/mm.2007.43},
}
This record lives at https://refs.drheap.org/conway2007amd/ and will keep doing so.