26.5 Adaptive clocking in the POWER9™ processor for voltage droop protection
The work
| Authors | Michael S. Floyd; Phillip J. Restle; Michael A. Sperling; Pawel Owczarczyk; Eric J. Fluhr; Joshua Friedrich; Paul Muench; Timothy E. Diemoz; Pierce Chuang; Christos Vezyrtzis |
|---|---|
| Editors | |
| Type | misc |
| Year | 2017 |
| Citekey | floyd2017265 |
Where it appeared
| Published in | Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference |
|---|---|
| Publisher | Institute of Electrical and Electronics Engineers |
| Pages | 444--445 |
Identifiers
| DOI | 10.1109/isscc.2017.7870452 |
|---|---|
| OpenAlex | W2594678906 |
Access
| Landing page | https://doi.org/10.1109/isscc.2017.7870452 |
|---|
From OpenAlex, which stores abstracts as an index of words and their positions: what is shown is rebuilt from that, and reads fluently whether or not it is what the author wrote.
Abstract
Increasing transistor counts in modern processors can create instantaneous changes in current, driving nanosecond-speed supply voltage (VDD) droops that require extra guardband for correct product operation. The POWER9 processor uses an adaptive clock strategy to reduce timing margin needed during power supply droop events by embedding analog voltage-droop monitors (VDMs) that direct a digital phase-locked loop (DPLL) to immediately reduce clock frequency in response.
How it got here
| How it got here | agent via openalex |
|---|---|
| Added | 2026-10-27 19:06 UTC |
| Not denied by | a person 2026-10-29 17:12 UTC |
Cite it as
@misc{floyd2017265,
title = {26.5 Adaptive clocking in the POWER9™ processor for voltage droop protection},
author = {Michael S. Floyd and Phillip J. Restle and Michael A. Sperling and Pawel Owczarczyk and Eric J. Fluhr and Joshua Friedrich and Paul Muench and Timothy E. Diemoz and Pierce Chuang and Christos Vezyrtzis},
year = {2017},
journal = {Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference},
publisher = {Institute of Electrical and Electronics Engineers},
pages = {444--445},
doi = {10.1109/isscc.2017.7870452},
}
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