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Digital Device Error Rate Trends in Advanced CMOS Technologies
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Abstract
In this paper, data are presented from test chips in four technology nodes. With this data, the trends in single event effects as feature sizes shrink are studied. Some of the trends discussed include upset thresholds, shrinking cross sections, multiple bit upsets, and per bit error rate trends. Also included in this paper is some of the first ever heavy ion data from a 65 nm CMOS technology. With data from the 250 nm, 180 nm, 90 nm, and 65 nm technology nodes, the past, present, and future of what the radiation effects community has dealt with and will be dealing with when it comes to single event effects is presented
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Cite it as
@article{gadlage2006digital,
title = {Digital Device Error Rate Trends in Advanced CMOS Technologies},
author = {Matthew J. Gadlage and Paul H. Eaton and Joseph M. Benedetto and Marty Carts and Vivian Zhu and Thomas L. Turflinger},
year = {2006},
journal = {IEEE Transactions on Nuclear Science},
publisher = {Institute of Electrical and Electronics Engineers},
volume = {53},
number = {6},
pages = {3466--3471},
doi = {10.1109/tns.2006.886212},
}