Spatial avoidance of hardware faults using FPGA partial reconfiguration of tile-based soft processors
The work
| Authors | Clint Gauer; Brock J. LaMeres; David Racek |
|---|---|
| Editors | |
| Type | misc |
| Year | 2010 |
| Citekey | gauer2010spatial |
Where it appeared
| Published in | IEEE Aerospace Conference (AERO) |
|---|---|
| Publisher | Institute of Electrical and Electronics Engineers |
| Pages | 1--11 |
Identifiers
| DOI | 10.1109/aero.2010.5446663 |
|---|---|
| OpenAlex | W1968395020 |
Access
| Landing page | https://doi.org/10.1109/aero.2010.5446663 |
|---|
From OpenAlex, which stores abstracts as an index of words and their positions: what is shown is rebuilt from that, and reads fluently whether or not it is what the author wrote.
Abstract
This paper presents the design of a many-core computer architecture with fault detection and recovery using partial reconfiguration of an FPGA. The FPGA fabric is partitioned into tiles which contain homogenous soft processors. At any given time, three processors are configured in triple modulo redundancy to detect faults. Spare processors are brought online to replace faulted tiles in real time. A recovery procedure involving partial reconfiguration is used to repair faulted tiles. This type of approach has the advantage of recovering from faults in both the circuit fabric and the configuration RAM of an FPGA in addition to spatially avoiding permanently damaged regions of the chip.
How it got here
| How it got here | agent via openalex |
|---|---|
| Added | 2026-10-27 15:36 UTC |
| Not denied by | a person 2026-10-29 17:12 UTC |
Cite it as
@misc{gauer2010spatial,
title = {Spatial avoidance of hardware faults using FPGA partial reconfiguration of tile-based soft processors},
author = {Clint Gauer and Brock J. LaMeres and David Racek},
year = {2010},
journal = {IEEE Aerospace Conference (AERO)},
publisher = {Institute of Electrical and Electronics Engineers},
pages = {1--11},
doi = {10.1109/aero.2010.5446663},
}
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