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Runtime reconfigurable memory hierarchy in embedded scalable platforms
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Abstract
In heterogeneous systems-on-chip, the optimal choice of the cache-coherence model for a loosely-coupled accelerator may vary at each invocation, depending on workload and system status. We propose a runtime adaptive algorithm to manage the coherence of accelerators. The algorithm's choices are based on the combination of static and dynamic features of the active accelerators and their workloads. We evaluate the algorithm by leveraging our FPGA-based platform for rapid SoC prototyping. Experimental results, obtained through the deployment of a multi-core and multi-accelerator system that runs Linux SMP, show the benefits of our approach in terms of execution time and memory accesses.
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Cite it as
@misc{giri2019runtime,
title = {Runtime reconfigurable memory hierarchy in embedded scalable platforms},
author = {Davide Giri and Paolo Mantovani and Luca P. Carloni},
year = {2019},
journal = {Asia and South Pacific Design Automation Conference (ASP-DAC)},
pages = {719--726},
doi = {10.1145/3287624.3288755},
}