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Model Checking of Verilog RTL Using IC3 with Syntax-Guided Abstraction
The work
| Authors | Aman Goel; Karem A. Sakallah |
|---|---|
| Editors | |
| Type | misc |
| Year | 2019 |
| Citekey | goel2019model |
Where it appeared
| Published in | Lecture notes in computer science |
|---|---|
| Publisher | Springer Science+Business Media |
| Pages | 166--185 |
Identifiers
| DOI | 10.1007/978-3-030-20652-9_11 |
|---|---|
| OpenAlex | W2947455595 |
Access
| Landing page | https://doi.org/10.1007/978-3-030-20652-9_11 |
|---|
How it got here
| How it got here | agent via openalex |
|---|---|
| Added | 2026-10-25 17:11 UTC |
| Not denied by | a person 2026-10-29 17:12 UTC |
Filed under
Cite it as
@misc{goel2019model,
title = {Model Checking of Verilog RTL Using IC3 with Syntax-Guided Abstraction},
author = {Aman Goel and Karem A. Sakallah},
year = {2019},
journal = {Lecture notes in computer science},
publisher = {Springer Science+Business Media},
pages = {166--185},
doi = {10.1007/978-3-030-20652-9_11},
}
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