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PCH framework for IP runtime security verification
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Abstract
Untrusted third-party vendors and manufacturers have raised security concerns in hardware supply chain. Among all existing solutions, formal verification methods provide powerful solutions in detection malicious behaviors at the pre-silicon stage. However, little work have been done towards built-in hardware runtime verification at the post-silicon stage. In this paper, a runtime formal verification framework is proposed to evaluate the trust of hardware during its execution. This framework combines the symbolic execution and SAT solving methods to validate the user defined properties. The proposed framework has been demonstrated on an FPGA platform using an SoC design with untrusted IPs. The experimentation results show that the proposed approach can provide high-level security assurance for hardware at runtime.
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Cite it as
@misc{guo2017pch,
title = {PCH framework for IP runtime security verification},
author = {Xiaolong Guo and Raj Gautam Dutta and Jiaji He and Yier Jin},
year = {2017},
journal = {Asian Hardware Oriented Security and Trust Symposium (AsianHOST)},
pages = {79--84},
doi = {10.1109/asianhost.2017.8353999},
}