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On-the-fly programmable hardware for networks

The work

AuthorsIlija Hadžić; Jonathan M. Smith; W.S. Marcus
Editors
Typemisc
Year1998
Also known ashadzic2002onthefly
Citekeyhadzic1998onthefly

Where it appeared

Published inGlobecom
PublisherInstitute of Electrical and Electronics Engineers
Volume2
Pages821--826

From OpenAlex, which stores abstracts as an index of words and their positions: what is shown is rebuilt from that, and reads fluently whether or not it is what the author wrote.

Abstract

Ongoing research in adaptive protocols and active networks has presumed that flexibility is offered exclusively through software systems, and the performance implications have generated considerable skepticism. The programmable protocol processing pipeline (P4) exploits the dynamic reconfigurability of RAM based field programmable gate arrays (FPGAs) to provide both hardware performance and dynamic functionality to network components. We use forward error correction (FEC) as an example of a protocol processing function which we insert and remove from the protocol stack on an as-needed basis. Our measurements show that the P4 is able to process the data stream at OC-3 (155 Mbps) link rate, and consequently improve the TCP performance in noisy environments.

How it got here

How it got hereagent via openalex
Added2026-10-28 15:31 UTC
Not denied bya person 2026-10-29 17:12 UTC

Cite it as

@misc{hadzic1998onthefly,
  title        = {On-the-fly programmable hardware for networks},
  author       = {Ilija Hadžić and Jonathan M. Smith and W.S. Marcus},
  year         = {1998},
  journal      = {Globecom},
  publisher    = {Institute of Electrical and Electronics Engineers},
  volume       = {2},
  pages        = {821--826},
  doi          = {10.1109/glocom.1998.776848},
}

This record lives at https://refs.drheap.org/hadzic1998onthefly/ and will keep doing so. It used to be called hadzic2002onthefly, and those addresses still resolve to this one.