A 3.6 GHz 16-Core SPARC SoC Processor in 28 nm
The work
| Authors | Jason M. Hart; Hoyeol Cho; Yuefei Ge; Gregory Gruber; Dawei Huang; Changku Hwang; Daisy Jian; Tim Johnson; Georgios K. Konstadinidis; Venkat Krishnaswamy; L. Kwong; Robert P. Masleid; Rakesh Mehta; Umesh Gajanan Nawathe; Aparna Ramachandran; Hari Sathianathan; Yongning Sheng; Jinuk Luke Shin; Sebastian Turullols; Zuxu Qin; King Yen |
|---|---|
| Editors | |
| Type | article |
| Year | 2014 |
| Also known as | hart2013ghz |
| Citekey | hart2014ghz |
Where it appeared
| Published in | IEEE Journal of Solid-State Circuits |
|---|---|
| Publisher | Institute of Electrical and Electronics Engineers |
| Volume | 49 |
| Issue | 1 |
| Pages | 19--31 |
Identifiers
| DOI | 10.1109/jssc.2013.2284648 |
|---|---|
| OpenAlex | W2158074071 |
Access
| Landing page | https://doi.org/10.1109/jssc.2013.2284648 |
|---|
From OpenAlex, which stores abstracts as an index of words and their positions: what is shown is rebuilt from that, and reads fluently whether or not it is what the author wrote.
Abstract
The 3.6 GHz SPARC T5 processor is Oracle's next generation CMT SoC processor implemented in TSMC's 28 nm process with 1.5 billion transistors. Significant performance improvements were made by doubling the previous generations number of cores to 16 and L3 cache size to 8 MB while increasing bandwidth by nearly 3×. Power efficiency was improved through features like DVFS, core-pair cycle skipping and SerDes power scaling. The SPARC T5 processor has been designed to fit in systems that can scale from 1 to 8 sockets, or 128 to 1024 threads, in glueless fashion. The diverse system-level bandwidth requirements of up to 5.65 TB/sec in these systems are met by advanced SERDES design that handles up to 30 dB loss in an area and power efficient manner. The different thermal envelopes of these systems are addressed by power management features that span software, system and chip design.
How it got here
| How it got here | agent via openalex |
|---|---|
| Added | 2026-10-27 19:11 UTC |
| Not denied by | a person 2026-10-29 17:12 UTC |
Cite it as
@article{hart2014ghz,
title = {A 3.6 GHz 16-Core SPARC SoC Processor in 28 nm},
author = {Jason M. Hart and Hoyeol Cho and Yuefei Ge and Gregory Gruber and Dawei Huang and Changku Hwang and Daisy Jian and Tim Johnson and Georgios K. Konstadinidis and Venkat Krishnaswamy and L. Kwong and Robert P. Masleid and Rakesh Mehta and Umesh Gajanan Nawathe and Aparna Ramachandran and Hari Sathianathan and Yongning Sheng and Jinuk Luke Shin and Sebastian Turullols and Zuxu Qin and King Yen},
year = {2014},
journal = {IEEE Journal of Solid-State Circuits},
publisher = {Institute of Electrical and Electronics Engineers},
volume = {49},
number = {1},
pages = {19--31},
doi = {10.1109/jssc.2013.2284648},
}
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