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SEU tolerant device, circuit and processor design
The work
| Authors | William Heidergott |
|---|---|
| Editors | |
| Type | misc |
| Year | 2005 |
| Citekey | heidergott2005seu |
Where it appeared
| Published in | Proceedings - ACM IEEE Design Automation Conference |
|---|---|
| Publisher | Association for Computing Machinery |
| Pages | 5 |
Identifiers
| DOI | 10.1145/1065579.1065586 |
|---|---|
| OpenAlex | W2099692688 |
Access
| Landing page | https://doi.org/10.1145/1065579.1065586 |
|---|
From OpenAlex, which stores abstracts as an index of words and their positions: what is shown is rebuilt from that, and reads fluently whether or not it is what the author wrote.
Abstract
Development of highly reliable and available systems requires consideration of the occurrence of single event upsets, the effects they have on system performance, and strategies for their prevention and mitigation. Methods of systems engineering process and the application and validation of techniques for fault tolerance are discussed as elements in the elimination and mitigation of single event upsets.
How it got here
| How it got here | agent via openalex |
|---|---|
| Added | 2026-10-26 00:56 UTC |
| Not denied by | a person 2026-10-29 17:12 UTC |
Cite it as
@misc{heidergott2005seu,
title = {SEU tolerant device, circuit and processor design},
author = {William Heidergott},
year = {2005},
journal = {Proceedings - ACM IEEE Design Automation Conference},
publisher = {Association for Computing Machinery},
pages = {5},
doi = {10.1145/1065579.1065586},
}
This record lives at https://refs.drheap.org/heidergott2005seu/ and will keep doing so.