Soft-Error Vulnerability of Sub-100-nm Flip-Flops
The work
| Authors | Tino Heijmen |
|---|---|
| Editors | |
| Type | misc |
| Year | 2008 |
| Citekey | heijmen2008softerror |
Where it appeared
| Published in | IEEE International On-Line Testing Symposium (IOLTS) |
|---|---|
| Pages | 247--252 |
Identifiers
| DOI | 10.1109/iolts.2008.12 |
|---|---|
| OpenAlex | W2119795588 |
Access
| Landing page | https://doi.org/10.1109/iolts.2008.12 |
|---|
From OpenAlex, which stores abstracts as an index of words and their positions: what is shown is rebuilt from that, and reads fluently whether or not it is what the author wrote.
Abstract
The soft-error vulnerability of flip-flops has become an important factor in IC reliability in sub-100-nm CMOS technologies. In the present work the soft-error rate (SER) of a 65-nm flip-flop has been investigated with the use of alpha-accelerated testing. Simulations have been applied to study the flip-flop SER sensitivity in detail. Furthermore, an easy-to-use approach is presented to make an accurate estimation of the contribution of flip-flops to the SER of an IC. The method is applicable to frequencies well below 1 GHz. The approach is based on a set of expressions for the timing vulnerability factor (TVF) of the master and slave latches of the flip-flop. With this approach it is possible to make an accurate estimation of the flip-flop SER parameters.
How it got here
| How it got here | agent via openalex |
|---|---|
| Added | 2026-10-26 00:27 UTC |
| Not denied by | a person 2026-10-29 17:12 UTC |
Cite it as
@misc{heijmen2008softerror,
title = {Soft-Error Vulnerability of Sub-100-nm Flip-Flops},
author = {Tino Heijmen},
year = {2008},
journal = {IEEE International On-Line Testing Symposium (IOLTS)},
pages = {247--252},
doi = {10.1109/iolts.2008.12},
}
This record lives at https://refs.drheap.org/heijmen2008softerror/ and will keep doing so.