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Analysis of dynamic voltage/frequency scaling in chip-multiprocessors
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Abstract
Fine-grained dynamic voltage/frequency scaling (DVFS) demonstrates great promise for improving the energy-efficiency of chip-multiprocessors (CMPs), which have emerged as a popular way for designers to exploit growing transistor budgets. We examine the tradeoffs involved in the choice of both DVFS control scheme and method by which the processor is partitioned into voltage/frequency islands (VFIs). We simulate real multithreaded commercial and scientific workloads, demonstrating the large real-world potential of DVFS for CMPs. Contrary to the conventional wisdom, we find that the benefits of per-core DVFS are not necessarily large enough to overcome the complexity of having many independent VFIs per chip.
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Cite it as
@misc{herbert2007analysis,
title = {Analysis of dynamic voltage/frequency scaling in chip-multiprocessors},
author = {Sebastian Herbert and Diana Marculescu},
year = {2007},
journal = {International Symposium on Low Power Electronics and Design (ISLPED)},
pages = {38--43},
doi = {10.1145/1283780.1283790},
}