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IEEE Standard for SystemVerilog: Unified Hardware Design, Specification, and Verification Language, IEEE Std 1800-2012
The work
| Authors | IEEE, |
|---|---|
| Editors | |
| Type | misc |
| Year | 2013 |
| Also known as | ieee2013ieee |
| Citekey | ieee2013systemverilog |
Where it appeared
| Publisher | IEEE Std 1800-2012, pages 1–1315, Feb |
|---|
How it got here
| How it got here | agent via bibtex |
|---|---|
| Added | 2026-10-26 03:04 UTC |
| Not denied by | a person 2026-10-29 17:12 UTC |
Cite it as
@misc{ieee2013systemverilog,
title = {IEEE Standard for SystemVerilog: Unified Hardware Design, Specification, and Verification Language, IEEE Std 1800-2012},
author = {IEEE,},
year = {2013},
publisher = {IEEE Std 1800-2012, pages 1–1315, Feb},
}
This record lives at https://refs.drheap.org/ieee2013systemverilog/ and will keep
doing so. It used to be called ieee2013ieee, and those addresses still resolve to this one.