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IEEE Standard for SystemVerilog--Unified Hardware Design, Specification, and Verification Language
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Abstract
The definition of the language syntax and semantics for SystemVerilog, which is a unified hardware design, specification, and verification language, is provided. This standard includes support for modeling hardware at the behavioral, register transfer level (RTL), and gate-level abstraction levels, and for writing testbenches using coverage, assertions, object-oriented programming, and constrained random verification. The standard also provides application programming interfaces (APIs) to foreign programming languages.
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Cite it as
@misc{ieee2017systemverilog,
title = {IEEE Standard for SystemVerilog--Unified Hardware Design, Specification, and Verification Language},
year = {2017},
doi = {10.1109/ieeestd.2018.8299595},
}