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A 0.8 μ 100-MHz 2-D DCT core processor

The work

AuthorsYi-Feng Jang; Jinn-Nang Kao; Jinn-Shiang Yang; Po-Chuang Huang
Editors
Typearticle
Year1994
Citekeyjang1994100mhz

Where it appeared

Published inIEEE Transactions on Consumer Electronics
PublisherInstitute of Electrical and Electronics Engineers
Volume40
Issue3
Pages703--710

Identifiers

DOI10.1109/30.320861
OpenAlexW2138545996

Access

Landing pagehttps://doi.org/10.1109/30.320861

From OpenAlex, which stores abstracts as an index of words and their positions: what is shown is rebuilt from that, and reads fluently whether or not it is what the author wrote.

Abstract

The discrete cosine transform (DCT) has been commonly adopted in many transformation applications such as image, video, and facsimile. A VLSI architecture and implementation of a high speed 2-dimensional DCT core processor with 0.8 /spl mu/ technology is presented. This architecture applies a fast DCT algorithm and multiplier-accumulator based on the distributed algorithm, which has contributed to reduce the hardware requirement and to achieve high speed operation. The transpose memory inserted between each dimension of DCT is partitioned in order to reduce further hardware overhead. Furthermore, this 2-dimensional DCT scheme satisfies the accuracy specification of CCITT recommendation MPEG.>

How it got here

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Added2026-10-27 13:40 UTC
Not denied bya person 2026-10-29 17:12 UTC

Cite it as

@article{jang1994100mhz,
  title        = {A 0.8 μ 100-MHz 2-D DCT core processor},
  author       = {Yi-Feng Jang and Jinn-Nang Kao and Jinn-Shiang Yang and Po-Chuang Huang},
  year         = {1994},
  journal      = {IEEE Transactions on Consumer Electronics},
  publisher    = {Institute of Electrical and Electronics Engineers},
  volume       = {40},
  number       = {3},
  pages        = {703--710},
  doi          = {10.1109/30.320861},
}

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