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Voter insertion algorithms for FPGA designs using triple modular redundancy
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Abstract
Triple Modular Redundancy (TMR) is a common reliability technique for mitigating single event upsets (SEUs) in FPGA designs operating in radiation environments. For FPGA systems that employ configuration scrubbing, majority voters are needed in all feedback paths to ensure proper synchronization between the TMR replicates. Synchronization voters, however, consume additional resources and impact system timing. This paper will introduce and contrast four algorithms for inserting synchronization voters while automatically performing TMR. The area cost and timing impact of each algorithm on a number of circuit benchmarks will be reported. This paper will demonstrate that one of the algorithms provides the best overall timing performance results with an average 9.8% increase in critical path length over a triplicated design without voters. Another algorithm provides far better area results at a slightly higher timing cost (an average 2.1% area increase over a triplicated design without voters).
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Cite it as
@misc{johnson2010voter,
title = {Voter insertion algorithms for FPGA designs using triple modular redundancy},
author = {Jonathan Johnson and Michael Wirthlin},
year = {2010},
journal = {ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA)},
pages = {249--258},
doi = {10.1145/1723112.1723154},
}