SEU-resistant SHA-256 design for security in satellites

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Abstract

Satellites currently play a fundamental role in communications and are also used in modern military operations. Given their importance, satellites should not rely their security on the uniqueness and obscurity of their systems. However, it is not trivial to implement cryptographic mechanisms due to high energy particles coming from space, which are the main cause of single event upsets (SEUs). Therefore, besides stringent constraints on area, power, energy and performance, satellites architectures must provide SEU-resistance. This research proposes and analyzes various architectures for SHA-256 hash function which are of utmost importance to ensure secure communications. Furthermore, in contrast to previous work, the proposed architectures are able to detect and correct errors. We show that a scheme employing Hamming codes to protect the main registers of SHA-256 leads to a better trade-off in terms of area, performance and power consumption, compared to the traditional triple modular redundancy (TMR). When implemented on an Altera Cyclone II FPGA, this approach demands 3657 LEs and consumes 126.18 mW of dynamic power. This can be translated to the utilization of 2.3 times as much area and 1.5 times as much power as the non-fault tolerant SHA-256 implementation. These results are crucial for supporting present and future embedded security in satellites, which demand both highly constrained and SEU-resistant designs.