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Seamless SoC Verification Using Virtual Platforms: An Industrial Case Study
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Abstract
As SoC (System-on-Chip) complexity continues to increase, function/performance verification is required in the middle of design process (before tape-out) to reduce the possible risks ranging from over-design to non-compliance with the design specifications. In this paper, we propose a seamless SoC verification. The proposed methodology exploits a modern virtual platform (VP) technology which can combine high-level C++ firmware, timing-accurate SystemC models, and RTL (register-transfer level) designs. Thus, the full-chip level verification can be done at any design stages in the whole development process. With experimental results, this paper shows the benefits and lessons of using VPs.
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@misc{kang2019seamless,
title = {Seamless SoC Verification Using Virtual Platforms: An Industrial Case Study},
author = {Kyungsu Kang and Sang‐Ho Park and Byeongwook Bae and Jungyun Choi and SungGil Lee and Byunghoon Lee and Jong-Bae Lee},
year = {2019},
journal = {Design, Automation, and Test in Europe},
pages = {1204--1205},
doi = {10.23919/date.2019.8715128},
}