Mechanically verifying a family of multiplier circuits

The work

AuthorsDeepak Kapur; M. Subramaniam
Editors
Typeinproceedings
Year1996
Citekeykapur1996mechanically

Where it appeared

Published inComputer Aided Verification (CAV)
PublisherSpringer Berlin Heidelberg
Pages135--146

Identifiers

DOI10.1007/3-540-61474-5_64
ISSN0302-9743
ISBN978-3-540-61474-6

Related

Distinct frombryant1986graphbased
Distinct fromburch1992symbolic
Distinct fromkocher1996timing
Distinct frommanjrekar2025automating
Distinct fromyang2025forword

From crossref.

Abstract

A methodology for mechanically verifying a family of parameterized multiplier circuits, including many well-known multiplier circuits such as the linear array, the Wallace tree and the 7-3 multiplier is proposed. A top level specification for these multipliers is obtained by abstracting the commonality in their behavior. The behavioral correctness of any multiplier in the family can be mechanically verified by a uniform proof strategy. Proofs of properties are done by rewriting and induction using an automated theorem prover RRL (Rewrite Rule Laboratory).

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Added2026-09-16 18:34 UTC
Approved bya person 2026-09-16 20:47 UTC

Cite it as

@inproceedings{kapur1996mechanically,
  title        = {Mechanically verifying a family of multiplier circuits},
  author       = {Deepak Kapur and M. Subramaniam},
  year         = {1996},
  booktitle    = {Computer Aided Verification (CAV)},
  publisher    = {Springer Berlin Heidelberg},
  pages        = {135--146},
  isbn         = {978-3-540-61474-6},
  issn         = {0302-9743},
  doi          = {10.1007/3-540-61474-5_64},
}

This record lives at https://refs.drheap.org/kapur1996mechanically/ and will keep doing so.