Soft-Error Characterization and Hardening Trade-offs in Static PCHB Asynchronous Circuits

The work

AuthorsRamya Karri; Srija Rasoori; Ashiq A. Sakib
Editors
Typemisc
Year2026
Citekeykarri2026softerror

Identifiers

arXiv2607.10788 from its landing_page_url

Access

Landing pagehttps://arxiv.org/abs/2607.10788

Related

Distinct fromburlyaev2015design
Distinct fromelshehaby2023susceptibility
Distinct frommanohar1995quasidelayinsensitive
Distinct frommartin1985delayinsensitive
Distinct fromxue2024using

From bibtex.

Abstract

Pre-Charge Half Buffer (PCHB) is a promising asynchronous digital design paradigm for harsh-environment operation; however, its soft-error characteristics remain largely unexplored. This paper presents a systematic soft-error characterization and hardening trade-off analysis for static PCHB circuits. A controlled transistor-level fault-injection framework is developed to extract polarity-dependent critical charge at internal nodes. Vulnerability nodes are identified based on extensive simulation. Four mitigation strategies, double-sided Schmitt trigger, single-sided Schmitt trigger, transmission-gate reinforcement, and duplication-based redundancy, are implemented and evaluated across five representative PCHB cells. Comprehensive resilience-overhead comparisons in delay, energy, and area are reported, leading to architecture-specific hardening guidelines for robust static PCHB design.

A copy is held

pdf, 1015.5 kB. Not published — it may be under copyright. The facts and links here are.

How it got here

How it got hereagent via bibtex
Added2026-09-16 05:13 UTC
Approved bya person 2026-09-16 09:11 UTC

Filed under

the-switch-or-the-curve

Cite it as

@misc{karri2026softerror,
  title        = {Soft-Error Characterization and Hardening Trade-offs in Static PCHB Asynchronous Circuits},
  author       = {Ramya Karri and Srija Rasoori and Ashiq A. Sakib},
  year         = {2026},
}

This record lives at https://refs.drheap.org/karri2026softerror/ and will keep doing so.