A Charge Domain P-8T SRAM Compute-In-Memory with Low-Cost DAC/ADC Operation for 4-bit Input Processing
The work
| Title | A Charge Domain P-8T SRAM Compute-In-Memory with Low-Cost DAC/ADC Operation for 4-bit Input Processing |
|---|---|
| Authors | Joonhyung Kim; Kyeongho Lee; Jongsun Park |
| Type | conference paper |
| Year | 2022 |
| Citekey | kim2022charge |
Where it appeared
| Published in | Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design |
|---|---|
| Publisher | Association for Computing Machinery |
| Volume | 55 |
| Pages | 1--6 |
Identifiers
| DOI | 10.1145/3531437.3539718 |
|---|---|
| OpenAlex | W4285676410 |
Access
| Landing page | https://doi.org/10.1145/3531437.3539718 |
|---|---|
| Free full text | https://arxiv.org/pdf/2211.16008 |
Abstract
This paper presents a low cost PMOS-based 8T (P-8T) SRAM Compute-In-Memory (CIM) architecture that efficiently per-forms the multiply-accumulate (MAC) operations between 4-bit input activations and 8-bit weights. First, bit-line (BL) charge-sharing technique is employed to design the low-cost and reliable digital-to-analog conversion of 4-bit input activations in the pro-posed SRAM CIM, where the charge domain analog computing provides variation tolerant and linear MAC outputs. The 16 local arrays are also effectively exploited to implement the analog mul-tiplication unit (AMU) that simultaneously produces 16 multipli-cation results between 4-bit input activations and 1-bit weights. For the hardware cost reduction of analog-to-digital converter (ADC) without sacrificing DNN accuracy, hardware aware system simulations are performed to decide the ADC bit-resolutions and the number of activated rows in the proposed CIM macro. In addition, for the ADC operation, the AMU-based reference col-umns are utilized for generating ADC reference voltages, with which low-cost 4-bit coarse-fine flash ADC has been designed. The 256×80 P-8T SRAM CIM macro implementation using 28nm CMOS process shows that the proposed CIM shows the accuracies of 91.46% and 66.67% with CIFAR-10 and CIFAR-100 dataset, respectively, with the energy efficiency of 50.07-TOPS/W.
Copy held
| Kind | PDF, 948.5 kB |
|---|---|
| Retrieved | 2026-08-08 |
| Held | local, for personal reference |
| Where it came from | https://arxiv.org/pdf/2211.16008 |
Where this came from
| How it got here | the agent went looking · found via openalex |
|---|---|
| First seen | 2026-08-04 |
| Record | reviewed by a person |
| Approved | 2026-08-08 |
Cite it as
@inproceedings{kim2022charge,
title = {A Charge Domain P-8T SRAM Compute-In-Memory with Low-Cost DAC/ADC Operation for 4-bit Input Processing},
author = {Joonhyung Kim and Kyeongho Lee and Jongsun Park},
year = {2022},
booktitle = {Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design},
volume = {55},
pages = {1--6},
publisher = {Association for Computing Machinery},
doi = {10.1145/3531437.3539718},
url = {https://arxiv.org/pdf/2211.16008},
}
This record lives at https://refs.drheap.org/kim2022charge/ and will keep doing so.