Niagara: A 32-Way Multithreaded Sparc Processor
The work
| Authors | Poonacha Kongetira; Kathirgamar Aingaran; Kunle Olukotun |
|---|---|
| Editors | |
| Type | article |
| Year | 2005 |
| Citekey | kongetira2005niagara |
Where it appeared
| Published in | IEEE Micro |
|---|---|
| Publisher | Institute of Electrical and Electronics Engineers |
| Volume | 25 |
| Issue | 2 |
| Pages | 21--29 |
Identifiers
| DOI | 10.1109/mm.2005.35 |
|---|---|
| OpenAlex | W2022740893 |
Access
| Landing page | https://doi.org/10.1109/mm.2005.35 |
|---|
From OpenAlex, which stores abstracts as an index of words and their positions: what is shown is rebuilt from that, and reads fluently whether or not it is what the author wrote.
Abstract
The Niagara processor implements a thread-rich architecture designed to provide a high-performance solution for commercial server applications. This is an entirely new implementation of the Sparc V9 architectural specification, which exploits large amounts of on-chip parallelism to provide high throughput. The hardware supports 32 threads with a memory subsystem consisting of an on-board crossbar, level-2 cache, and memory controllers for a highly integrated design that exploits the thread-level parallelism inherent to server applications, while targeting low levels of power consumption.
How it got here
| How it got here | agent via openalex |
|---|---|
| Added | 2026-10-27 17:29 UTC |
| Not denied by | a person 2026-10-29 17:12 UTC |
Cite it as
@article{kongetira2005niagara,
title = {Niagara: A 32-Way Multithreaded Sparc Processor},
author = {Poonacha Kongetira and Kathirgamar Aingaran and Kunle Olukotun},
year = {2005},
journal = {IEEE Micro},
publisher = {Institute of Electrical and Electronics Engineers},
volume = {25},
number = {2},
pages = {21--29},
doi = {10.1109/mm.2005.35},
}
This record lives at https://refs.drheap.org/kongetira2005niagara/ and will keep doing so.