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A Low-Noise Wideband Digital Phase-Locked Loop Based on a Coarse–Fine Time-to-Digital Converter With Subpicosecond Resolution

The work

AuthorsMinjae Lee; Mohammad Esmaeil Heidari; A.A. Abidi
Editors
Typearticle
Year2009
Citekeylee2009lownoise

Where it appeared

Published inIEEE Journal of Solid-State Circuits
PublisherInstitute of Electrical and Electronics Engineers
Volume44
Issue10
Pages2808--2816

From OpenAlex, which stores abstracts as an index of words and their positions: what is shown is rebuilt from that, and reads fluently whether or not it is what the author wrote.

Abstract

This paper presents the design of a digital PLL which uses a high-resolution time-to-digital converter (TDC) for wide loop bandwidth. The TDC uses a time amplification technique to reduce the quantization noise down to less than 1 ps root mean square (RMS). Additionally TDC input commutation reduces low-frequency spurs due to inaccurate TDC scaling factor in a counter-assisted digital PLL. The loop bandwidth is set to 400 kHz with a 25 MHz reference. The in-band phase noise contribution from the TDC is -116 dBc/Hz, the phase noise is -117 dBc/Hz at high band (1.8 GHz band) 400 kHz offset, and the RMS phase error is 0.3deg.

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Added2026-10-27 18:58 UTC
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Cite it as

@article{lee2009lownoise,
  title        = {A Low-Noise Wideband Digital Phase-Locked Loop Based on a Coarse–Fine Time-to-Digital Converter With Subpicosecond Resolution},
  author       = {Minjae Lee and Mohammad Esmaeil Heidari and A.A. Abidi},
  year         = {2009},
  journal      = {IEEE Journal of Solid-State Circuits},
  publisher    = {Institute of Electrical and Electronics Engineers},
  volume       = {44},
  number       = {10},
  pages        = {2808--2816},
  doi          = {10.1109/jssc.2009.2028753},
}

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