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SMIV: A 16-nm 25-mm² SoC for IoT With Arm Cortex-A53, eFPGA, and Coherent Accelerators
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Abstract
Emerging Internet of Things (IoT) devices necessitate system-on-chips (SoCs) that can scale from ultralow power always-on (AON) operation, all the way up to less frequent high-performance tasks at high energy efficiency. Specialized accelerators are essential to help meet these needs at both ends of the scale, but maintaining workload flexibility remains an important goal. This article presents a 25-mm2SoC in 16-nm FinFET technology which demonstrates targeted, flexible acceleration of key compute-intensive kernels spanning machine learning (ML), DSP, and cryptography. TheSMIVSoC includes a dedicated AON sub-system, a dual-core Arm Cortex-A53 CPU cluster, an SoC-attached embedded field-programmable gate array (eFPGA) array, and a quad-core cache-coherent accelerator (CCA) cluster. Measurement results demonstrate: 1) 1236\(\times \)power envelope, from 1.1 mW (only AON cluster), up to 1.36 W (whole SoC at maximum throughput); 2) 5.5–28.9\(\times \)energy efficiency gain from offloading compute kernels from A53 to eFPGA; 3) 2.94\(\times \)latency improvement using coherent memory access (CCA cluster); and 4) 55\(\times \)MobileNetV1 energy per inference improvement on CCA compared to the CPU baseline. The overall flexibility-efficiency range on SMIV spans measured energy efficiencies of 1\(\times \)(dual-core A53), 3.1\(\times \)(A53 with SIMD), 16.5\(\times \)(eFPGA), 54.9\(\times \)(CCA), and 256\(\times \)(AON) at a peak efficiency of 4.8 TOPS/W.
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@article{lee2021smiv,
title = {SMIV: A 16-nm 25-mm² SoC for IoT With Arm Cortex-A53, eFPGA, and Coherent Accelerators},
author = {Sae Kyu Lee and Paul N. Whatmough and Marco Donato and Glenn G. Ko and David M. Brooks and Gu-Yeon Wei},
year = {2021},
journal = {IEEE Journal of Solid-State Circuits},
publisher = {Institute of Electrical and Electronics Engineers},
volume = {57},
number = {2},
pages = {639--650},
doi = {10.1109/jssc.2021.3115466},
}