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The Stanford Dash multiprocessor

Where it appeared

Published inComputer
PublisherIEEE Computer Society
Volume25
Issue3
Pages63--79

Identifiers

DOI10.1109/2.121510
OpenAlexW2127547524

From OpenAlex, which stores abstracts as an index of words and their positions: what is shown is rebuilt from that, and reads fluently whether or not it is what the author wrote.

Abstract

The overall goals and major features of the directory architecture for shared memory (Dash) are presented. The fundamental premise behind the architecture is that it is possible to build a scalable high-performance machine with a single address space and coherent caches. The Dash architecture is scalable in that it achieves linear or near-linear performance growth as the number of processors increases from a few to a few thousand. This performance results from distributing the memory among processing nodes and using a network with scalable bandwidth to connect the nodes. The architecture allows shared data to be cached, significantly reducing the latency of memory accesses and yielding higher processor utilization and higher overall performance. A distributed directory-based protocol that provides cache coherence without compromising scalability is discussed in detail. The Dash prototype machine and the corresponding software support are described.>

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Added2026-10-27 07:07 UTC
Not denied bya person 2026-10-29 17:12 UTC

Cite it as

@article{lenoski1992stanford,
  title        = {The Stanford Dash multiprocessor},
  author       = {Daniel E. Lenoski and James P. Laudon and Kourosh Gharachorloo and Wolf-Dietrich Weber and Anoop Gupta and John LeRoy Hennessy and Mark Horowitz and Monica S. Lam},
  year         = {1992},
  journal      = {Computer},
  publisher    = {IEEE Computer Society},
  volume       = {25},
  number       = {3},
  pages        = {63--79},
  doi          = {10.1109/2.121510},
}

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