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Built-in Clock Domain Crossing (CDC) test and diagnosis in GALS systems
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Abstract
The purpose of this paper is to present a novel built-in Clock Domain Crossing (CDC) test and diagnosis methodology for Globally Asynchronous, Locally Synchronous (GALS) systems. The methodology allows design and prototype validation, low maintenance and repair costs, and production / lifetime at-speed test. Moreover, high resolution diagnosis is obtained, to identify which device(s) and/or communication channel(s) is (are) faulty. This is not trivial in GALS systems, for which the CDC issue is challenging. The underlying principle of the proposed methodology is to embed a CDC test and diagnosis (CDC T&D) structure in each locally synchronous domain. Complete device-to-device communication channels are tested, including transceivers, buses, and board connectors. Identical test patterns (generated to detect static (stuck-at, shorts and open faults) and dynamic (crosstalk) faults) are used in each FPGA. The proposed CDC T&D methodology is validated in a case study, the acquisition electronics of a complex multi-board, multibus, multi-FPGA (nine Xilinx™ xc2v4000-4bf957) system. Test and validation results are presented.
@misc{leong2010builtin,
title = {Built-in Clock Domain Crossing (CDC) test and diagnosis in GALS systems},
author = {C. Leong and P. Machado and Vasco Bexiga and J.P. Teixeira and I.C. Teixeira and J. C. Silva and Pedro Lousa and J. Varela},
year = {2010},
pages = {72--77},
doi = {10.1109/ddecs.2010.5491815},
}