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Analog/mixed-signal design challenges in 7-nm CMOS and beyond
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Abstract
The economics of CMOS scaling remain lucrative with 7-nm mobile SoCs expected to be commercialized in 2018. Driven by careful design/technology co-optimization, modest reduction in fin, gate, and interconnect pitch as well as process innovations continue to offer compelling node-to-node power, performance, area, and cost benefits to advance logic and SRAM to the next foundry node. However, analog/mixed-signal circuits do not fully realize these improvements. They become more cumbersome to design, having worse parasitic resistance and capacitance, stronger layout-dependent effects, and layout growth in some situations. Furthermore, early adopters of these cutting-edge finFET nodes must cope with the complications of design concurrent with technology development for shorter product time-to-market. We provide an overview of the key process technology elements enabling 7 nm and beyond to address analog/mixed-signal design challenges. From this insight, we offer layout guidelines aimed to reduce design vulnerability to technology and model immaturity.
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Cite it as
@misc{loke2018analogmixedsignal,
title = {Analog/mixed-signal design challenges in 7-nm CMOS and beyond},
author = {Alvin L. S. Loke and Da Yang and Tin Tin Wee and Jonathan L. Holland and Patrick Isakanian and K. Rim and Sam Yang and Jacob S. Schneider and Giri Nallapati and Sreeker Dundigal and Hasnain Lakdawala and Behnam Amelifard and Chulkyu Lee and B.P. McGovern and Paul S. Holdaway and Xiaohua Kong and Burton M. Leary},
year = {2018},
journal = {IEEE Custom Integrated Circuits Conference (CICC)},
pages = {1--8},
doi = {10.1109/cicc.2018.8357060},
}