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VLSI implementation of inverse discrete cosine transformer and motion compensator for MPEG2 HDTV video decoding

The work

AuthorsT. Masaki; Y. Morimoto; Takao Onoye; Isao Shirakawa
Editors
Typearticle
Year1995
Citekeymasaki1995vlsi

Where it appeared

Published inIEEE Transactions on Circuits and Systems for Video Technology
PublisherInstitute of Electrical and Electronics Engineers
Volume5
Issue5
Pages387--395

Identifiers

DOI10.1109/76.473552
OpenAlexW2021647244

From OpenAlex, which stores abstracts as an index of words and their positions: what is shown is rebuilt from that, and reads fluently whether or not it is what the author wrote.

Abstract

An MPEG2 video decoder core dedicated to MP@HL (Main Profile at High Level) images is described with the main theme focused on an inverse discrete cosine transformer and a motion compensator. By means of various novel architectures, the inverse discrete cosine transformer achieves a high throughput, and the motion compensator performs different types of picture prediction modes employed by the MPEG2 algorithm. The decoder core, implemented in the total chip area of 22.0 mm/sup 2/ by a 0.6-/spl mu/m triple-metal CMOS technology, processes a macroblock within 3.84 /spl mu/s, and therefore is capable of decoding HDTV (1920/spl times/1152 pels) images in real time.>

How it got here

How it got hereagent via openalex
Added2026-10-27 14:03 UTC
Not denied bya person 2026-10-29 17:12 UTC

Cite it as

@article{masaki1995vlsi,
  title        = {VLSI implementation of inverse discrete cosine transformer and motion compensator for MPEG2 HDTV video decoding},
  author       = {T. Masaki and Y. Morimoto and Takao Onoye and Isao Shirakawa},
  year         = {1995},
  journal      = {IEEE Transactions on Circuits and Systems for Video Technology},
  publisher    = {Institute of Electrical and Electronics Engineers},
  volume       = {5},
  number       = {5},
  pages        = {387--395},
  doi          = {10.1109/76.473552},
}

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