C. Batten

3 references under this name, matched as it is written. Somebody else may write under it too, and the same person may appear here spelled another way.

CIFER: A Cache-Coherent 12-nm 16-mm2 SoC With Four 64-Bit RISC-V Application Cores, 18 32-Bit RISC-V Compute Cores, and a 1541 LUT6/mm2 Synthesizable eFPGA

A. Li and others (2023) · Institute of Electrical and Electronics Engineers (IEEE)

Towards gradually typed hardware description languages

P. Pan and others (2023) · Rem

PyMTL3: A Python Framework for Open-Source Hardware Modeling, Generation, Simulation, and Verification

S. Jiang and others (2020) · Institute of Electrical and Electronics Engineers (IEEE)