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CIFER: A Cache-Coherent 12-nm 16-mm2 SoC With Four 64-Bit RISC-V Application Cores, 18 32-Bit RISC-V Compute Cores, and a 1541 LUT6/mm2 Synthesizable eFPGA
The work
| Authors | A. Li; T.-J. Chang; F. Gao; T. Ta; G. Tziantzioulis; Y. Ou; M. Wang; J. Tu; K. Xu; P. Jackson; A. Ning; G. Chirkov; M. Orenes-Vera; S. Agwa; X. Yan; E. Tang; J. Balkind; C. Batten; D. Wentzlaff |
|---|---|
| Editors | |
| Type | misc |
| Year | 2023 |
| Also known as | anon2023cifer |
| Citekey | li2023cifer |
Where it appeared
| Publisher | Institute of Electrical and Electronics Engineers (IEEE) |
|---|
Identifiers
| DOI | 10.1109/lssc.2023.3303111 |
|---|
How it got here
| How it got here | agent via unpaywall |
|---|---|
| Added | 2026-10-27 07:08 UTC |
| Not denied by | a person 2026-10-29 17:12 UTC |
Cite it as
@misc{li2023cifer,
title = {CIFER: A Cache-Coherent 12-nm 16-mm2 SoC With Four 64-Bit RISC-V Application Cores, 18 32-Bit RISC-V Compute Cores, and a 1541 LUT6/mm2 Synthesizable eFPGA},
author = {A. Li and T.-J. Chang and F. Gao and T. Ta and G. Tziantzioulis and Y. Ou and M. Wang and J. Tu and K. Xu and P. Jackson and A. Ning and G. Chirkov and M. Orenes-Vera and S. Agwa and X. Yan and E. Tang and J. Balkind and C. Batten and D. Wentzlaff},
year = {2023},
publisher = {Institute of Electrical and Electronics Engineers (IEEE)},
doi = {10.1109/lssc.2023.3303111},
}
This record lives at https://refs.drheap.org/li2023cifer/ and will keep
doing so. It used to be called anon2023cifer, and those addresses still resolve to this one.