F. Ahmad
1 reference under this name, matched as it is written. Somebody else may write under it too, and the same person may appear here spelled another way.
A 0.5–9.5-GHz, 1.2-µs Lock-Time Fractional-N DPLL With 1.25% UI Period Jitter in 16-nm CMOS for Dynamic Frequency and Core-Count Scaling
F. Ahmad and others (2017) · Institute of Electrical and Electronics Engineers (IEEE)